The present invention relates to the electrical, electronic, and computer arts, and more specifically, to fabrication of semiconductor wafers.
Presently, semiconductor wafers are fabricated by deposition and etching of materials on a substrate, usually silicon. Materials are first deposited and etched to form the front end of line (FEOL) circuitry such as individual transistors, then additional layers of material are deposited and etched to provide intermediate circuitry and finally the back end of line (BEOL) interconnects including vias. BEOL interconnects are created using mostly a dual damascene scheme for copper metallization with a TiN hard mask to define the trench and self-aligned via. In some cases, single damascene is used. In both types of damascene process, a nitride cap layer or “Nblock” layer is deposited onto copper circuitry formed in an underlayer, then an oxide layer (often, an ultra-low K layer) is deposited over the Nblock and a hard mask goes on over the oxide layer.